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Integrated circuit TSV 3D packaging reliability test methods guideline
Scope of Application：
This document provides guidelines for reliability test methods used in the process development verification of Through-Silicon Via (TSV) 3D packaging.
This document applies to process validation tests for TSV 3D packaging manufactured using pre-via, mid-via, and post-via processes.
Basic information
Standard No：GB/Z 43510-2023
Standard Name： 集成电路TSV三维封装可靠性试验方法指南
English Name：Integrated circuit TSV 3D packaging reliability test methods guideline
Standard Status：In force
Release Date：2023-12-28
Effective Date：2024-04-01
Language of Publication：Simplified Chinese
Publication Information
Number of pages：12
Number of words：17 K
Other Information
Technical Committees：National Technical Committee for Standardization of Nanotechnology (SAC/TC 279)
Proposed Unit：Chinese Academy of Science
Application Dept：State Administration for Market Supervision and Administration, State Standardization Administration
